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Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog by Vaibbhav
- Item No : 156970722762
- Condition : Brand New
- Brand : No brand Info
- Seller : the_nile
- Current Bid : US $182.81
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* Item Description
- By Vaibbhav Taraate. He completed his M.Tech. He has over 15 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.
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