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Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog by Vaibbhav
- Item No : 156970722762
- Condition : Brand New
- Brand : No brand Info
- Seller : the_nile
- Current Bid : US $183.24
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* Item Description
- By Vaibbhav Taraate. Author Vaibbhav Taraate. This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies.
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