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High-Level Verification: Methods and Tools for Verification of System-Level Desi
- Item No : 146748247966
- Condition : Brand New
- Brand : No brand Info
- Seller : the_nile
- Current Bid : US $132.62
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* Item Description
- This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing.
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